View CY7C1480BV25-167AXC_4969211.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

cy7c1480bv25 cy7c1482bv25, cy7c1486bv25 72-mbit (2 m 36/4 m 18/1 m 72) pipelined sync sram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-15143 rev. *h revised may 4, 2011 72-mbit (2 m 36/4 m 18/1 m 72) pipelined sync sram features supports bus operation up to 250 mhz available speed grades are 250, 200, and 167 mhz registered inputs and outputs for pipelined operation 2.5-v core power supply 2.5-v i/o operation fast clock-to-output time ? 3.0 ns (for 250 mhz device) provide high performance 3-1-1-1 access rate user selectable burst counter supporting intel ? pentium ? interleaved or linear burst sequences separate processor and controller address strobes synchronous self timed writes asynchronous output enable single cycle chip deselect cy7c1480bv25, cy7c1482bv25 available in jedec-standard pb-free 100-pin thin quad flat pack (tqfp), pb-free and non pb-free 165-ball fine-pitch ball grid array (fbga) package. cy7c1486bv25 available in pb-free and non-pb-free 209-ball fbga package ieee 1149.1 jtag-compatible boundary scan ?zz? sleep mode option functional description the cy7c1480bv25/cy7c1482bv25/cy7c1486bv25 [1] sram integrates 2 m 36/4 m 18/1 m 72 sram cells with advanced synchronous peripheral circuitry and a two-bit counter for internal burst operation. all synchronous inputs are gated by registers controlled by a positive-edge-triggered clock input (clk). the synchronous inputs include all addresses, all data inputs, address-pipelining chip enable (ce 1 ), depth-expansion chip enables (ce 2 and ce 3 ), burst control inputs (adsc , adsp , and adv ), write enables (bw x , and bwe ), and global write (gw ). asynchronous inputs include the output enable (oe ) and the zz pin. addresses and chip enables are registered at rising edge of clock when either address strobe processor (adsp ) or address strobe controller (adsc ) is active. subsequent burst addresses can be internally generated as controlled by the advance pin (adv ). address, data inputs, and write controls are registered on-chip to initiate a self timed write cycle. this part supports byte write operations (see pin definitions on page 8 and truth table on page 11 for further details). write cycles can be one to two or four bytes wide, as controlled by the byte write control inputs. when it is active low, gw writes all bytes. selection guide description 250 mhz 200 mhz 167 mhz unit maximum access time 3.0 3.0 3.4 ns maximum operating current 450 450 400 ma maximum complementary metal oxide semiconductor (cmos) standby current 120 120 120 ma note 1. for best practices recommendations, refer to the cypress application note an1064, sram system guidelines . [+] feedback
cy7c1480bv25 cy7c1482bv25, cy7c1486bv25 document number: 001-15143 rev. *h page 2 of 34 logic block diagram ? cy7c1480bv25 (2 m 36) logic block diagram ? cy7c1482bv25 (4 m 18) address register adv clk burst counter and logic clr q1 q0 adsp adsc mode bwe gw ce 1 ce 2 ce 3 oe enable register output registers sense amps output buffers e pipelined enable input registers a 0, a1, a bw b bw c bw d bw a memory array dqs dqp a dqp b dqp c dqp d sleep control zz a [1:0] 2 dq a, dqp a byte write register dq b, dqp b byte write register dq c, dqp c byte write register dq d, dqp d byte write register dq a, dqp a byte write driver dq b, dqp b byte write driver dq c, dqp c byte write driver dq d ,dqp d byte write driver a 0, a1, a address register adv clk burst counter and logic clr q1 q0 adsc bw b bw a ce 1 dq b, dqp b write register dq a, dqp a write register enable register oe sense amps memory array adsp 2 mode ce2 ce3 gw bwe pipelined enable dqs dqp a dqp b output registers input registers e dq a, dqp a write driver output buffers dq b, dqp b write driver a[1:0] zz sleep control [+] feedback
cy7c1480bv25 cy7c1482bv25, cy7c1486bv25 document number: 001-15143 rev. *h page 3 of 34 logic block diagram ? cy7c1486bv25 (1 m 72) bw d bw c bw b bw a bwe gw ce1 ce2 ce3 oe enable register pipelined enable address register adv clk binary counter clr q1 q0 adsp adsc mode a 0, a1,a a[1:0] bw f bw e bw h bw g dqs dqp a dqp b dqp c dqp d dqp e dqp f dqp g dqp h output registers memory array output buffers e dq a , dqp a write driver dq b , dqp b write driver dq c , dqp c write driver dq d , dqp d write driver input registers byte a write driver dq e , dqp e write driver dq f , dqp f write driver dq g , dqp g write driver dq h , dqp h write driver sense amps sleep control zz dq a , dqp a write driver dq b , dqp b write driver dq c , dqp c write driver dq d , dqp d write driver dq e , dqp e write driver dq f , dqp f write driver dq f , dqp f write driver dq h , dqp h write driver [+] feedback
cy7c1480bv25 cy7c1482bv25, cy7c1486bv25 document number: 001-15143 rev. *h page 4 of 34 contents pin configurations ........................................................... 5 pin definitions .................................................................. 8 functional overview ........................................................ 9 single read accesses ................................................ 9 single write accesse s initiated by adsp ................... 9 single write accesses initiate d by adsc ................. 10 burst sequences ....................................................... 10 sleep mode ............................................................... 10 interleaved burst address table (mode = floating or v dd ) .............................................. 10 linear burst address table (mode = gnd) ................................................................ 10 zz mode electrical characteristics ............................... 10 truth table ...................................................................... 11 truth table for read/write ............................................ 12 truth table for read/write ............................................ 12 truth table for read/write ............................................ 13 ieee 1149.1 serial boundary sc an (jtag) ... ........... .... 14 disabling the jtag feature ...................................... 14 tap controller state diagram ....................................... 14 test access port (tap) ............................................. 14 tap controller block diagram ...................................... 14 performing a tap r eset .......... .............. .......... 14 tap registers ...................................................... 14 tap instruction set ................................................... 15 tap ac switching characteristics ............................... 16 2.5 v tap ac test conditions ....................................... 17 2.5 v tap ac output load equivalent ......................... 17 tap dc electrical characteristics and operating conditions ..................................................... 17 identification register definitions ................................ 17 scan register sizes ....................................................... 18 identification codes ....................................................... 18 boundary scan exit order (2 m 36) ........................... 19 boundary scan exit order (4 m 18) ........................... 19 boundary scan exit order (1 m 72) ........................... 20 maximum ratings ........................................................... 21 operating range ............................................................. 21 electrical characteristics ............................................... 21 capacitance .................................................................... 22 thermal resistance ........................................................ 22 switching characteristics .............................................. 23 switching waveforms .................................................... 24 ordering information ...................................................... 28 ordering code definitions ..... .................................... 28 package diagrams .......................................................... 29 acronyms ........................................................................ 32 document conventions ................................................. 32 units of measure ....................................................... 32 document history page ................................................. 33 sales, solutions, and legal information ...................... 34 worldwide sales and design s upport ......... .............. 34 products .................................................................... 34 psoc solutions ......................................................... 34 [+] feedback
cy7c1480bv25 cy7c1482bv25, cy7c1486bv25 document number: 001-15143 rev. *h page 5 of 34 pin configurations dqp b dq b dq b v ddq v ssq dq b dq b dq b dq b v ssq v ddq dq b dq b v ss nc v dd zz dq a dq a v ddq v ssq dq a dq a dq a dq a v ssq v ddq dq a dq a dqp a dqp c dq c dqc v ddq v ssq dq c dq c dq c dq c v ssq v ddq dq c dq c v dd nc v ss dq d dq d v ddq v ssq dq d dq d dq d dq d v ssq v ddq dq d dq d dqp d a a ce 1 ce 2 bw d bw c bw b bw a ce 3 v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 cy7c1480bv25 (2 m 36) nc a a a a a 1 a 0 a a v ss v dd a a a a a a a a a nc nc v ddq v ssq nc dqp a dq a dq a v ssq v ddq dq a dq a v ss nc v dd zz dq a dq a v ddq v ssq dq a dq a nc nc v ssq v ddq nc nc nc nc nc nc v ddq v ssq nc nc dq b dq b v ssq v ddq dq b dq b v dd nc v ss dq b dq b v ddq v ssq dq b dq b dqp b nc v ssq v ddq nc nc nc a a ce 1 ce 2 nc nc bw b bw a ce 3 v dd v ss clk gw bwe oe adsc adsp adv a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 mode cy7c1482bv25 (4 m 18) nc a a a a a a 1 a 0 a a v ss v dd a a a a a a a a mode a figure 1. 100-pin tqfp pinout [+] feedback
cy7c1480bv25 cy7c1482bv25, cy7c1486bv25 document number: 001-15143 rev. *h page 6 of 34 pin configurations (continued) 165-ball fbga (15 17 1.4 mm) pinout cy7c1480bv25 (2 m 36) cy7c1482bv25 (4 m 18) 234 567 1 a b c d e f g h j k l m n p r tdo nc/288m nc/144m dqp c dq c dqp d nc dq d ce 1 bw b ce 3 bw c bwe a ce2 dq c dq d dq d mode nc dq c dq c dq d dq d dq d a a v ddq bw d bw a clk gw v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss a v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck v ss tdi a a dq c v ss dq c v ss dq c dq c nc v ss v ss v ss v ss nc v ss a1 dq d dq d nc nc v ddq v ss tms 891011 a adv a adsc nc oe adsp a nc/576m v ss v ddq nc/1g dqp b v ddq v dd dq b dq b dq b nc dq b nc dq a dq a v dd v ddq v dd v ddq dq b v dd nc v dd dq a v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq dq a v ddq a a v ss a a a dq b dq b dq b zz dq a dq a dqp a dq a a v ddq a a0 a v ss 234 567 1 a b c d e f g h j k l m n p r tdo nc/288m nc/144m nc nc dqp b nc dq b a ce 1 nc ce 3 bw b bwe a ce2 nc dq b dq b mode nc dq b dq b nc nc nc a a v ddq nc bw a clk gw v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss a v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck a0 v ss tdi a a dq b v ss nc v ss dq b nc nc v ss v ss v ss v ss nc v ss a1 dq b nc nc nc v ddq v ss tms 891011 a adv a adsc a oe adsp a nc/576m v ss v ddq nc/1g dqp a v ddq v dd nc dq a dq a nc nc nc dq a nc v dd v ddq v dd v ddq dq a v dd nc v dd nc v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq nc v ddq a a v ss a a a dq a nc nc zz dq a nc nc dq a a v ddq a [+] feedback
cy7c1480bv25 cy7c1482bv25, cy7c1486bv25 document number: 001-15143 rev. *h page 7 of 34 pin configurations (continued) cy7c1486bv25 (1 m 72) 209-ball fbga (14 22 1.76 mm) pinout a b c d e f g h j k l m n p r t u v w 123456789 11 10 dq g dq g dq g dq g dq g dq g dq g dq g dq c dq c dq c dq c nc dqp g dq h dq h dq h dq h dq d dq d dq d dq d dqp d dqp c dq c dq c dq c dq c nc dq h dq h dq h dq h dqp h dq d dq d dq d dq d dq b dq b dq b dq b dq b dq b dq b dq b dq f dq f dq f dq f nc dqp f dq a dq a dq a dq a dq e dq e dq e dq e dqp a dqp b dq f dq f dq f dq f nc dq a dq a dq a dq a dqp e dq e dq e dq e dq e a adsp adv a nc nc a aa a a aa aa a a1 a0 a aa aa a nc/144m nc/288m nc/576m gw nc nc bws b bws f bws e bws a bws c bws g bws d bws h tms tdi tdo tck nc nc mode nc v ss v ss nc clk nc v ss v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v ss v ss v ss v ss v ss v ss v ss v ss nc/1g v dd nc oe ce 3 ce 1 ce 2 adsc bwe v ss v ss v ss v ss v ss v ss v ss zz v ss v ss v ss v ss nc v ddq v ss v ss nc v ss v ss v ss v ss v ss v ss nc v ss v ddq v ddq v ddq v ddq v ddq nc v ddq v ddq v ddq v ddq nc v ddq v ddq v ddq v ddq nc v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq [+] feedback
cy7c1480bv25 cy7c1482bv25, cy7c1486bv25 document number: 001-15143 rev. *h page 8 of 34 pin definitions pin name i/o description a 0 , a 1 , a input- synchronous address inputs used to select one of the address locations . sampled at the rising edge of the clk if adsp or adsc is active low, and ce 1 , ce 2 , and ce 3 are sampled active. a1: a0 are fed to the two-bit counter. bw a , bw b , bw c , bw d , bw e , bw f , bw g , bw h input- synchronous byte write select (bws) inputs, active low . qualified with bwe to conduct byte writes to the sram. sampled on the rising edge of clk. gw input- synchronous global write enable input, active low . when asserted low on the rising edge of clk, a global write is conducted (all bytes are written, regardless of the values on bw x and bwe ). bwe input- synchronous byte write enable (bwe ) input, active low . sampled on the rising edge of clk. this signal must be asserted low to conduct a byte write. clk input- clock clock input . captures all synchronous inputs to the device. also increments the burst counter when adv is asserted low duri ng a burst operation. ce 1 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select or deselect the device. adsp is ignored if ce 1 is high. ce 1 is sampled only when a new external address is loaded. ce 2 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select or deselect the device. ce 2 is sampled only when a new external address is loaded. ce 3 input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select or deselect the device. ce 3 is sampled only when a new external address is loaded. oe input- asynchronous output enable, asynchronous input, active low . controls the direction of the i/o pins. when low, the i/o pins behave as outputs. when deasserted high, i/o pins are tristated, and act as input data pins. oe is masked during the first clo ck of a read cycle when emerging from a deselected state. adv input- synchronous advance input signal, sampled on the rising edge of clk, active low . when asserted, it automatically increments the address in a burst cycle. adsp input- synchronous address strobe from processor, sampled on the rising edge of clk, active low . when asserted low, addresses presented to the device are captured in the address registers. a1: a0 are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. asdp is ignored when ce 1 is deasserted high. adsc input- synchronous address strobe from controller, sampled on the rising edge of clk, active low . when asserted low, addresses presented to the device are captured in the address registers. a1: a0 are also loaded into the burst counter. when adsp and adsc are both asserted, only adsp is recognized. zz input- asynchronous zz ?sleep? input, active high . when asserted high places the device in a non-time-critical ?sleep? condition with data integr ity preserved. for normal operation, this pin must be low or left floating. zz pin has an internal pull down. dqs, dqps i/o- synchronous bidirectional data i/o lines . as inputs, they feed into an on-chip data register that is triggered by the rising edge of clk. as outputs, they deliver the data contained in the memory location specified by the addresses presented during the previous cloc k rise of the read cycle. the direction of the pins is controlled by oe . when oe is asserted low, the pins behave as outputs. when high, dqs and dqp x are placed in a tristate condition. v dd power supply power supply inputs to the core of the device . v ss ground ground for the core of the device. v ssq [2] i/o ground ground for the i/o circuitry. v ddq i/o power supply power supply for the i/o circuitry . note 2. applicable for tqfp package. for bga package v ss serves as ground for the core and the i/o circuitry. [+] feedback
cy7c1480bv25 cy7c1482bv25, cy7c1486bv25 document number: 001-15143 rev. *h page 9 of 34 functional overview all synchronous inputs pass through input registers controlled by the rising edge of the clock. all data outputs pass through output registers controlled by the ri sing edge of the clock. maximum access delay from the clock rise (t co ) is 3.0 ns (250 mhz device). the cy7c1480bv25/cy7c1482bv25/cy7c1486bv25 supports secondary cache in systems using either a linear or interleaved burst sequence. the interleaved burst order supports pentium and i486 ? processors. the linear burst sequence is suited for processors that use a linear burst sequence. the burst order is user selectable, and is determined by sampling the mode input. accesses can be initiated with either the processor address strobe (adsp ) or the controller address strobe (adsc ). address advancement through the burst sequence is controlled by the adv input. a two-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. byte write operations are qualif ied with the byte write enable (bwe ) and byte write select (bw x ) inputs. a global write enable (gw ) overrides all byte write inputs and writes data to all four bytes. all writes are simplified with on-chip synchronous self-timed write circuitry. three synchronous chip selects (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) provide easy bank selection and output tristate control. adsp is ignored if ce 1 is high. single read accesses this access is initiated when the following conditions are satisfied at clock rise: (1) adsp or adsc is asserted low, (2) ce 1 , ce 2 , ce 3 are all asserted active, and (3) the write signals (gw , bwe ) are all deasserted high. adsp is ignored if ce 1 is high. the address presented to the address inputs (a) is stored into the address ad vancement logic and the address register while being presented to the memory array. the corresponding data is allowed to propagate to the input of the output registers. at the rising edge of the next clock the data is allowed to propagate through the output register and onto the data bus within 3.0 ns (250-mhz device) if oe is active low. the only exception occurs when the sram is emerging from a deselected state to a selected state; it s outputs are always tristated during the first cycle of the access. after the first cycle of the access, the outputs are controlled by the oe signal. consecutive single read cycles are supported. after the sram is deselected at clock rise by the chip select and either adsp or adsc signals, its output tristates immediately. single write accesses initiated by adsp this access is initiated when both of the following conditions are satisfied at clock rise: (1) adsp is asserted low, and (2) ce 1 , ce 2 , ce 3 are all asserted active. the address presented to a is loaded into the address register and the address advancement logic while being delivered to the memory array. the write signals (gw , bwe , and bw x ) and adv inputs are ignored during this first cycle. adsp -triggered write accesses require two clock cycles to complete. if gw is asserted low on th e second clock rise, the data presented to the dqs inputs is written into the corresponding address location in the memory array. if gw is high, then the bwe and bw x signals control the write operation. the cy7c1480bv25/cy7c1482bv25/cy7c1486bv25 provides byte write capabilit y that is described in the truth table for read/write on page 12 . asserting the byte write enable input (bwe ) with the selected byte write (bw x ) input, selectively writes to only the desired bytes. bytes not selected during a byte write operation remain unaltered. a synchronous self-timed write mechanism is provided to si mplify the write operations. because cy7c1480bv25/cy7c1482bv25/cy7c1486bv25 is a common i/o device, the output enable (oe ) must be deasserted high before presenting data to the dqs inputs. doing so tristates the output driv ers. as a safety precaution, dqs are automatically tris tated whenever a write cycle is detected, regardless of the state of oe . mode input static selects burst order . when tied to gnd selects linear burst sequence. when tied to v dd or left floating selects interleaved burst sequence. this is a strap pin and must remain static during device operation. mode pin has an internal pull up. tdo jtag serial output synchronous serial data out to the jtag circuit . delivers data on the negative edge of tck. if the jtag feature is not used, this pin mu st be disconnected. this pin is not available on tqfp packages. tdi jtag serial input synchronous serial data in to the jtag circuit . sampled on the rising edge of tck. if the jtag feature is not used, this pin can be disconnected or connected to v dd . this pin is not available on tqfp packages. tms jtag serial input synchronous serial data in to the jtag circuit . sampled on the rising edge of tck. if the jtag feature is not used, this pin can be disconnected or connected to v dd . this pin is not available on tqfp packages. tck jtag clock clock input to th e jtag circuitry . if the jtag feature is not used, this pin must be connected to v ss . this pin is not available on tqfp packages. nc - no connects . not internally connected to the die. 144m, 288m, 576m, and 1g are address expansion pins and are not inte rnally connected to the die. pin definitions (continued) pin name i/o description [+] feedback
cy7c1480bv25 cy7c1482bv25, cy7c1486bv25 document number: 001-15143 rev. *h page 10 of 34 single write accesses initiated by adsc adsc write accesses are initiated when the following conditions are satisfied: (1) adsc is asserted low, (2) adsp is deasserted high, (3) ce 1 , ce 2 , ce 3 are all asserted active, and (4) the appropriate combination of the write inputs (gw , bwe , and bw x ) are asserted active to conduct a write to the desired byte(s). adsc -triggered write accesses need a single clock cycle to complete. the address presented to a is loaded into the address register and the address advancement logic while being delivered to the memory array. the adv input is ignored during this cycle. if a global write is conducted, the data presented to the dqs is written into the corresponding address location in the memory core. if a byte write is co nducted, only the selected bytes are written. bytes not selected during a byte write operation remain unaltered. a synchronous self-timed write mechanism has been provided to simplify the write operations. because cy7c1480bv25/cy7c1482bv25/cy7c1486bv25 is a common i/o device, the output enable (oe ) must be deasserted high before presenting data to the dqs inputs. doing so tristates the output driv ers. as a safety precaution, dqs are automatically tristated whenev er a write cycle is detected, regardless of the state of oe . burst sequences the cy7c1480bv25/cy7c1482bv25/cy7c1486bv25 provides a two-bit wraparound counter, fed by a1: a0, that implements either an interleaved or linear burst sequence. the interleaved burst sequence is des igned specifically to support intel pentium applications. the linear burst sequence is designed to support processors that follow a linear burst sequence. the burst sequence is user selectable through the mode input. asserting adv low at clock rise auto matically increments the burst counter to the next addre ss in the burst sequence. both read and write burst operations are supported. sleep mode the zz input pin is asynchronous. asserting zz places the sram in a power conservation ?sleep? mode. two clock cycles are required to enter into or exit from this ?sleep? mode. while in this mode, data integrity is guaranteed. accesses pending when entering the ?sleep? mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected prior to entering the ?sleep? mode. ce 1 , ce 2 , ce 3 , adsp , and adsc must remain inactive for the duration of t zzrec after the zz input returns low. interleaved burst address table (mode = floating or v dd ) first address a1: a0 second address a1: a0 third address a1: a0 fourth address a1: a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) first address a1: a0 second address a1: a0 third address a1: a0 fourth address a1: a0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 zz mode electrical characteristics parameter description test conditions min max unit i ddzz sleep mode standby current zz > v dd ? ? 0.2 v ? 120 ma t zzs device operation to zz zz > v dd ? 0.2 v ? 2t cyc ns t zzrec zz recovery time zz < 0.2 v 2t cyc ?ns t zzi zz active to sleep current th is parameter is sampled ? 2t cyc ns t rzzi zz inactive to exit sleep curr ent this parameter is sampled 0 ? ns [+] feedback
cy7c1480bv25 cy7c1482bv25, cy7c1486bv25 document number: 001-15143 rev. *h page 11 of 34 truth table the truth table for cy7c1480bv25, cy7c1482bv25, and cy7c1486bv25 follows. [3, 4, 5, 6, 7] operation add. used ce 1 ce 2 ce 3 zz adsp adsc adv write oe clk dq deselect cycle, power down none h x x l x l x x x l-h tristate deselect cycle, power down none l l x l l x x x x l-h tristate deselect cycle, power down none l x h l l x x x x l-h tristate deselect cycle, power down none l l x l h l x x x l-h tristate deselect cycle, power down none l x h l h l x x x l-h tristate sleep mode, power down none x x x h x x x x x x tristate read cycle, begin burst external l h l l l x x x l l-h q read cycle, begin burst external l h l l l x x x h l-h tristate write cycle, begin burst external l h l l h l x l x l-h d read cycle, begin burst external l h l l h l x h l l-h q read cycle, begin burst external l h l l h l x h h l-h tristate read cycle, continue burst next x x x l h h l h l l-h q read cycle, continue burst next x x x l h h l h h l-h tristate read cycle, continue burst next h x x l x h l h l l-h q read cycle, continue burst next h x x l x h l h h l-h tristate write cycle, continue burst next x x x l h h l l x l-h d write cycle, continue burst next h x x l x h l l x l-h d read cycle, suspend burst current x x x l h h h h l l-h q read cycle, suspend burst current x x x l h h h h h l-h tristate read cycle, suspend burst current h x x l x h h h l l-h q read cycle, suspend burst current h x x l x h h h h l-h tristate write cycle, suspend burst current x x x l h h h l x l-h d write cycle, suspend burst current h x x l x h h l x l-h d notes 3. x = do not care, h = logic high, l = logic low. 4. write = l when any one or more byte write enable signals and bwe = l or gw = l. write = h when all byte write enable signals, bwe , gw = h. 5. the dq pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 6. the sram always initiates a read cycle when adsp is asserted, regardless of the state of gw , bwe , or bw x . writes may occur only on subsequent clocks after the adsp or with the assertion of adsc . as a result, oe must be driven high before the start of the write cycle to enable the outputs to tristate. oe is a do not care for the remainder of the write cycle 7. oe is asynchronous and is not sampled with the clock rise. it is masked internally during write cycles. during a read cycle all d ata bits are tristate when oe is inactive or when the device is deselected, a nd all data bits behave as outputs when oe is active (low). [+] feedback
cy7c1480bv25 cy7c1482bv25, cy7c1486bv25 document number: 001-15143 rev. *h page 12 of 34 truth table for read/write the read-write truth table for the cy7c1480bv25 follows. [8] function (cy7c1480bv25) gw bwe bw d bw c bw b bw a read h h x x x x read hlhhhh write byte a ? (dq a and dqp a )hlhhhl write byte b ? (dq b and dqp b )hlhhlh write bytes b, a h l h h l l write byte c ? (dq c and dqp c )hlhlhh write bytes c, a h l h l h l write bytes c, b h l h l l h write bytes c, b, a h l h l l l write byte d ? (dq d and dqp d )hllhhh write bytes d, a h l l h h l write bytes d, b h l l h l h write bytes d, b, a h l l h l l write bytes d, c h l l l h h write bytes d, c, a h l l l h l write bytes d, c, b h l l l l h write all bytes hlllll write all bytes l x x x x x truth table for read/write the read-write truth table for the cy7c1482bv25 follows. [8] function (cy7c1482bv25) gw bwe bw b bw a read h h x x read h l h h write byte a ? (dq a and dqp a )hlhl write byte b ? (dq b and dqp b )hllh write bytes b, a h l l l write all bytes h l l l write all bytes l x x x note 8. the dq pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. [+] feedback
cy7c1480bv25 cy7c1482bv25, cy7c1486bv25 document number: 001-15143 rev. *h page 13 of 34 truth table for read/write the read-write truth table for the cy7c1486bv25 follows. [9] function (cy7c1486bv25) gw bwe bw x read hhx read h l all bw = h write byte x ? (dq x and dqp x )hll write all bytes h l all bw = l write all bytes l x x note 9. bw x represents any byte write signal bw [0..7]. to enable any byte write bw x, a logic low signal must be applied at clo ck rise. any number of byte writes can be enabled at the same time for a supplied write. [+] feedback
cy7c1480bv25 cy7c1482bv25, cy7c1486bv25 document number: 001-15143 rev. *h page 14 of 34 ieee 1149.1 serial boundary scan (jtag) the cy7c1480bv25/cy7c1482bv25/cy7c1486bv25 incorporates a serial boundary scan test access port (tap). this port operates in accordance with ieee standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. these functions from the ieee specification are excluded because their inclusion places an added delay in the critical speed path of the sram . note that the tap controller functions in a manner that does not conflict with the operation of other devices using 1149.1 fully compliant taps. the tap operates using jedec-standard 2.5 v i/o logic levels. the cy7c1480bv25/cy7c1482bv25/cy7c1486bv25 contains a tap controller, instruction register, boundary scan register, bypass register, and id register. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap controller, tie tck low (v ss ) to prevent device clocking. tdi and tms are internally pulled up and may be unconnected. they may alternatively be connected to v dd through a pull up resistor. tdo must be left unconnected. at power up, the device comes up in a reset state, which does not interfere with the operation of the device. the 0/1 next to each state represents the value of tms at the rising edge of tck. test access port (tap) test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tc k. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input gives commands to the tap controller and is sampled on the rising edge of tck. you can leave this ball unconnected if the tap is not used. the ball is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi ball serially inputs information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. for information about loading the instruction register, see the tap controller state diagram . tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most significant bit (msb) of any register. (see tap controller block diagram .) test data-out (tdo) the tdo output ball is used to serially clock data-out from the registers. whether the output is active depends on the current state of the tap state machine. the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. (see tap controller state diagram .) performing a tap reset perform a reset by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and may be performed while the sram is operating. at power up, the tap is reset internally to ensure that tdo comes up in a high z state. tap registers registers are connected between the tdi and tdo balls to scan the data in and out of the sram test circuitry. only one register can be selected at a time through the instruction register. data is serially loaded into the tdi ball on the rising edge of tck. data is output on the tdo ball on the falling edge of tck. tap controller state diagram test-logic reset run-test/ idle select dr-scan select ir-scan capture-dr shift-dr capture-ir shift-ir exit1-dr pause-dr exit1-ir pause-ir exit2-dr update-dr exit2-ir update-ir 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 tap controller block diagra bypass register 0 instruction register 0 1 2 identication register 0 1 2 29 30 31 . . . boundary scan register 0 1 2 . . x . . . selection circuitry tck tms tap controller tdi tdo selection circuitry [+] feedback
cy7c1480bv25 cy7c1482bv25, cy7c1486bv25 document number: 001-15143 rev. *h page 15 of 34 instruction register three-bit instructions can be seri ally loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo balls as shown in the tap controller block diagram on page 14 . at power up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is plac ed in a reset state, as described in the previous section. when the tap controller is in t he capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to enable fault isolation of the board-le vel serial test data path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between the tdi and tdo balls. this shifts data through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bidirectional balls on the sram. the 36 configuration has a 73-bit-long register, and the 18 configuration has a 54-bit-long register. the boundary scan register is lo aded with the contents of the ram i/o ring when the tap contro ller is in the capture-dr state and is then placed between the tdi and tdo balls when the controller moves to the sh ift-dr state. the extest, sample/preload, and sample z instructions can be used to capture the conten ts of the i/o ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the re gister is connected to tdi and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr stat e when the idcode command is loaded in the instruction register . the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id regi ster has a vendor code and other information described in identification register definitions on page 17 . tap instruction set overview eight different instructions are possible with the three-bit instruction register. all co mbinations are listed in identification codes on page 18 . three of these instructions are listed as reserved and must not be used. the other five instructions are described in detail below. the tap controller used in this sram is not fully compliant to the 1149.1 convention because some of the mandatory 1149.1 instructions are not fully implemented. the tap controller cannot be used to load address data or control signals into the sram and cannot preload the i/o buffers. the sram does not implement the 1149.1 commands extest or intest or the preload portion of sample/preload; rather, it performs a capture of the i/o ring when these instructions are executed. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo balls. to execute the instruction after it is shift ed in, the tap controller must be moved into the update-ir state. extest extest is a mandatory 1149.1 instruction that is executed whenever the instruction regist er is loaded with all zeros. extest is not implemented in this sram tap controller, and therefore this device is not compliant to 1149.1. the tap controller does recognize an all-zero instruction. when an extest instruction is loaded into the instruction register, the sram responds as if a sample/preload instruction has been loaded. ther e is one difference between the two instructions. unlike the sample/preload instruction, extest places the sram outputs in a high z state. idcode the idcode instruction loads a vendor-specific, 32-bit code into the instruction register. it also places the instruction register between the tdi and tdo balls and shifts the idcode out of the device when the tap controller enters the shift-dr state. the idcode instruction is loaded into the instruction register at power up or whenever the tap controller is in a test logic reset state. sample z the sample z instruction connects the boundary scan register between the tdi and tdo balls when the tap controller is in a shift-dr state. it also places all sram outputs into a high z state. sample/preload sample/preload is a 1149.1 m andatory instruction. the preload portion of this instruction is not implemented, so the device tap controller is not fully 1149.1 compliant. when the sample/preload instruction is loaded into the instruction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register. be aware that the tap controller clock can only operate at a frequency up to 10 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possible that during the capture-dr state, an input or output may undergo a transition. the tap may then try to capture a signal while in transition (metastable state). this does not harm the device, but there is no guarantee as to the value that may be captured. repeatable results may not be possible. to guarantee that the boundary scan register captures the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controller?s capture setup plus hold time (t cs plus t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a [+] feedback
cy7c1480bv25 cy7c1482bv25, cy7c1486bv25 document number: 001-15143 rev. *h page 16 of 34 sample/preload instruction. if th is is an issue, it is still possible to capture all other signals and simply ignore the value of the clk captured in the boundary scan register. after the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo balls. note that because the preload part of the command is not implemented, putting the tap to the update-dr state while performing a sample/preload instruction has the same effect as the pause-dr command. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift- dr state, the bypass register is placed between the tdi and tdo balls. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. reserved these instructions are not im plemented but are reserved for future use. do not use these instructions. figure 2. tap timing tap ac switchi ng characteristics over the operating range [10, 11] parameter description min max unit clock t tcyc tck clock cycle time 50 ? ns t tf tck clock frequency ? 20 mhz t th tck clock high time 20 ? ns t tl tck clock low time 20 ? ns output times t tdov tck clock low to tdo valid ? 10 ns t tdox tck clock low to tdo invalid 0 ? ns setup times t tmss tms setup to tck clock rise 5 ? ns t tdis tdi setup to tck clock rise 5 ? ns t cs capture setup to tck rise 5 ? ns hold times t tmsh tms hold after tck clock rise 5 ? ns t tdih tdi hold after clock rise 5 ? ns t ch capture hold after clock rise 5 ? ns t tl test clock (tck) 123456 t est mode select (tms) t th test data-out (tdo) t cyc test data-in (tdi) t tmsh t tmss t tdih t tdis t tdox t tdov dont care undefined notes 10. t cs and t ch refer to the setup and hold time requirements of latching data from the boundary scan register. 11. test conditions are spec ified using the load in tap ac test conditions. t r /t f = 1 ns. [+] feedback
cy7c1480bv25 cy7c1482bv25, cy7c1486bv25 document number: 001-15143 rev. *h page 17 of 34 2.5 v tap ac test conditions input pulse levels................................................v ss to 2.5 v input rise and fall time .....................................................1 ns input timing reference levels...... .................................. 1.25 v output reference levels ............................................... 1.25 v test load termination supply voltage ........................... 1.25 v 2.5 v tap ac output load equivalent tdo 1.25v 20pf z = 50 o 50 (0 c < t a < +70 c; v dd = 2.5 v 0.125 v unless otherwise noted) [12] parameter description test conditions min max unit v oh1 output high voltage i oh = ?1.0 ma, v ddq = 2.5 v 1.7 ? v v oh2 output high voltage i oh = ?100 ? a, v ddq = 2.5 v 2.1 ? v v ol1 output low voltage i ol = 1.0 ma, v ddq = 2.5 v ? 0.4 v v ol2 output low voltage i ol = 100 ? a, v ddq = 2.5 v ? 0.2 v v ih input high voltage v ddq = 2.5 v 1.7 v dd + 0.3 v v il input low voltage v ddq = 2.5 v ?0.3 0.7 v i x input load current gnd ? v i ? v ddq ?5 5 ? a identification regi ster definitions instruction field cy7c1480bv25 (2 m 36) cy7c1482bv25 (4 m 18) cy7c1486bv25 (1 m 72) description revision number (31:29) 000 000 000 describes the version number device depth (28:24) 01011 01011 01011 reserved for internal use architecture/memory type(23:18) 000000 000000 000000 defines memory type and architecture bus width/density(17:12) 100100 010100 1 10100 defines width and density cypress jedec id code (11:1) 00000110100 00000110100 00000110100 enables unique identification of sram vendor id register presence indicator (0) 1 1 1 indicates the presence of an id register note 12. all voltages refer to v ss (gnd). [+] feedback
cy7c1480bv25 cy7c1482bv25, cy7c1486bv25 document number: 001-15143 rev. *h page 18 of 34 scan register sizes register name bit size ( 36) bit size ( 18) bit size ( 72) instruction 3 3 3 bypass 1 1 1 id 32 32 32 boundary scan order ? 165-ball fbga 73 54 ? boundary scan order ? 209-ball bga ? ? 112 identification codes instruction code description extest 000 captures the i/o ring contents. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operations. sample z 010 captures the i/o ring contents. pl aces the boundary scan regi ster between tdi and tdo. forces all sram output drivers to a high z state. reserved 011 do not use: this instru ction is reserved for future use. sample/preload 100 captures the i/o ring contents. places the boundary scan regi ster between tdi and tdo. does not affect sram operation. reserved 101 do not use: this instru ction is reserved for future use. reserved 110 do not use: this instru ction is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operations. [+] feedback
cy7c1480bv25 cy7c1482bv25, cy7c1486bv25 document number: 001-15143 rev. *h page 19 of 34 boundary scan exit order (2 m 36) bit # 165-ball id bit # 165-ball id bit # 165-ball id bit # 165-ball id 1c121r341l1061b8 2d1 22p2 42k11 62a7 3e1 23r4 43j11 63b7 4 d2 24 p6 44 k10 64 b6 5 e2 25 r6 45 j10 65 a6 6f1 26n6 46h11 66b5 7g1 27p11 47g11 67a5 8f2 28r8 48f11 68a4 9g2 29p3 49e11 69b4 10 j1 30 p4 50 d10 70 b3 11 k1 31 p8 51 d11 71 a3 12 l1 32 p9 52 c11 72 a2 13 j2 33 p10 53 g10 73 b2 14 m1 34 r9 54 f10 15 n1 35 r10 55 e10 16 k2 36 r11 56 a10 17 l2 37 n11 57 b10 18 m2 38 m11 58 a9 19 r1 39 l11 59 b9 20 r2 40 m10 60 a8 boundary scan exit order (4 m 18) bit # 165-ball id bit # 165-ball id bit # 165-ball id 1d219r837c11 2e220p338a11 3f2 21p4 39a10 4g2 22p8 40b10 5j1 23p9 41a9 6k1 24p10 42b9 7l1 25r9 43a8 8 m1 26 r10 44 b8 9n1 27r11 45a7 10 r1 28 m10 46 b7 11 r2 29 l10 47 b6 12 r3 30 k10 48 a6 13 p2 31 j10 49 b5 14 r4 32 h11 50 a4 15 p6 33 g11 51 b3 16 r6 34 f11 52 a3 17 n6 35 e11 53 a2 18 p11 36 d11 54 b2 [+] feedback
cy7c1480bv25 cy7c1482bv25, cy7c1486bv25 document number: 001-15143 rev. *h page 20 of 34 boundary scan exit order (1 m 72) bit # 209-ball id bit # 209-ball id bit # 209-ball id bit # 209-ball id 1 a1 29 t1 57 v10 85 c11 2a2 30t2 58u11 86c10 3 b1 31 u1 59 u10 87 b11 4b2 32u2 60t11 88b10 5c1 33v1 61t10 89a11 6c2 34v2 62r11 90a10 7 d1 35 w1 63 r10 91 a9 8d2 36w2 64p11 92u8 9 e1 37 t6 65 p10 93 a7 10 e2 38 v3 66 n11 94 a5 11 f1 39 v4 67 n10 95 a6 12 f2 40 u4 68 m11 96 d6 13 g1 41 w5 69 m10 97 b6 14 g2 42 v6 70 l11 98 d7 15 h1 43 w6 71 l10 99 k3 16 h2 44 u3 72 p6 100 a8 17 j1 45 u9 73 j11 101 b4 18 j2 46 v5 74 j10 102 b3 19 l1 47 u5 75 h11 103 c3 20 l2 48 u6 76 h10 104 c4 21 m1 49 w7 77 g11 105 c8 22 m2 50 v7 78 g10 106 c9 23 n1 51 u7 79 f11 107 b9 24 n2 52 v8 80 f10 108 b8 25 p1 53 v9 81 e10 109 a4 26 p2 54 w11 82 e11 110 c6 27 r2 55 w10 83 d11 111 b7 28 r1 56 v11 84 d10 112 a3 [+] feedback
cy7c1480bv25 cy7c1482bv25, cy7c1486bv25 document number: 001-15143 rev. *h page 21 of 34 maximum ratings exceeding the maximum ratings may impair the useful life of the device. these user guidelines are not tested. storage temperature ..... ............ ............... ?65 ? c to +150 ? c ambient temperature with power applied ..... .............. .............. .......... ?55 ? c to +125 ? c supply voltage on v dd relative to gnd ........?0.3 v to +3.6 v supply voltage on v ddq relative to gnd....... ?0.3 v to +v dd dc voltage applied to outputs in tristate ............................................?0.5 v to v ddq + 0.5 v dc input voltage .................................. ?0.5 v to v dd + 0.5 v current into outputs (low) ......................................... 20 ma static discharge voltage.......................................... > 2001 v (mil-std-883, method 3015) latch up current..................................................... > 200 ma operating range range ambient temperature v dd v ddq commercial 0 ? c to +70 ? c 2.5 v ? ? 5% / + 5% 2.5 v ? 5% to v dd industrial ?40 ? c to +85 ? c neutron soft error immunity parameter description test conditions typ max* unit lsbu logical single-bit upsets 25 c 361 394 fit/ mb lmbu logical multi-bit upsets 25 c 0 0.01 fit/ mb sel single event latch up 85 c 0 0.1 fit/ dev * no lmbu or sel events occurred during testing ; this column represents a statistical ? 2 , 95% confidence limit calculation. for more details refer to appli- cation note an 54908 ?accelerated neutron ser testing and calculation of terrestrial failure rates? electrical characteristics over the operating range [13, 14] parameter description test conditions min max unit v dd power supply voltage 2.375 2.625 v v ddq i/o supply voltage for 2.5 v i/o 2.375 v dd v v oh output high voltage for 2.5 v i/o, i oh = ?1.0 ma 2.0 ? v v ol output low voltage for 2.5 v i/o, i ol = 1.0 ma ? 0.4 v v ih input high voltage [13] for 2.5 v i/o 1.7 v dd + 0.3 v v v il input low voltage [13] for 2.5 v i/o ?0.3 0.7 v i x input leakage current except zz and mode gnd ? v i ? v ddq ?5 5 ? a input current of mode input = v ss ?30 ? ? a input = v dd ?5 ? a input current of zz input = v ss ?5 ? ? a input = v dd ?30 ? a i oz output leakage current gnd ? v i ? v ddq, output disabled ?5 5 ? a i dd [15] v dd operating supply current v dd = max, i out = 0 ma, f = f max = 1/t cyc 4.0-ns cycle, 250 mhz ? 450 ma 5.0-ns cycle, 200 mhz ? 450 ma 6.0-ns cycle, 167 mhz ? 400 ma notes 13. overshoot: v ih (ac) < v dd + 1.5 v (pulse width less than t cyc /2).undershoot: v il (ac) > ?2 v (pulse width less than t cyc /2). 14. power up: assumes a linear ramp from 0 v to v dd (min.) within 200 ms. during this time v ih < v dd and v ddq < v dd . 15. the operation current is calculated with 50% read cycle and 50% write cycle. [+] feedback
cy7c1480bv25 cy7c1482bv25, cy7c1486bv25 document number: 001-15143 rev. *h page 22 of 34 i sb1 automatic ce power down current?ttl inputs v dd = max, device deselected, v in ? v ih or v in ? v il , f = f max = 1/t cyc 4.0-ns cycle, 250 mhz ? 200 ma 5.0-ns cycle, 200 mhz ? 200 ma 6.0-ns cycle, 167 mhz ? 200 ma i sb2 automatic ce power down current?cmos inputs v dd = max, device deselected, v in ? 0.3 v or v in > v ddq ? 0.3 v, f = 0 all speeds ? 120 ma i sb3 automatic ce power down current?cmos inputs v dd = max, device deselected, or v in ? 0.3 v or v in > v ddq ? 0.3 v, f = f max = 1/t cyc 4.0-ns cycle, 250 mhz ? 200 ma 5.0-ns cycle, 200 mhz ? 200 ma 6.0-ns cycle, 167 mhz ? 200 ma i sb4 automatic ce power down current?ttl inputs v dd = max, device deselected, v in ? v ih or v in ? v il , f = 0 all speeds ? 135 ma capacitance tested initially and after any design or proc ess change that may affect these parameters. parameter description test conditions 100-pin tqfp package 165-ball fbga package 209-ball fbga package unit c address address input capacitance t a = 25 ? c, f = 1 mhz, v dd = 2.5 v v ddq = 2.5 v 666pf c data data input capacitance 5 5 5 pf c ctrl control input capacitance 8 8 8 pf c clk clock input capacitance 6 6 6 pf c io input/output capacitance 5 5 5 pf thermal resistance tested initially and after any design or proc ess change that may affect these parameters. parameter description test conditions 100-pin tqfp max 165-ball fbga max 209-ball fbga max unit ? ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia/jesd51. 24.63 16.3 15.2 ? c/w ? jc thermal resistance (junction to case) 2.28 2.1 1.7 ? c/w figure 3. ac test loads and waveforms electrical characteristics (continued) over the operating range [13, 14] parameter description test conditions min max unit output r = 1667 ? r = 1583 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v l = 1.25 v 2.5 v all input pulses v ddq gnd 90% 10% 90% 10% ? 1 ns ? 1 ns (c) 2.5 v i/o test load [+] feedback
cy7c1480bv25 cy7c1482bv25, cy7c1486bv25 document number: 001-15143 rev. *h page 23 of 34 switching characteristics over the operating range [16, 17] parameter description 250 mhz 200 mhz 167 mhz unit min max min max min max t power v dd (typical) to the first access [18] 1?1?1?ms clock t cyc clock cycle time 4.0 ? 5.0 ? 6.0 ? ns t ch clock high 2.0 ? 2.0 ? 2.4 ? ns t cl clock low 2.0 ? 2.0 ? 2.4 ? ns output times t co data output valid after clk rise ? 3.0 ? 3.0 ? 3.4 ns t doh data output hold after clk rise 1.3 ? 1.3 ? 1.5 ? ns t clz clock to low z [19, 20, 21] 1.3 ? 1.3 ? 1.5 ? ns t chz clock to high z [19, 20, 21] ? 3.0 ? 3.0 ? 3.4 ns t oev oe low to output valid ? 3.0 ? 3.0 ? 3.4 ns t oelz oe low to output low z [19, 20, 21] 0?0?0? ns t oehz oe high to output high z [19, 20, 21] ? 3.0 ? 3.0 ? 3.4 ns setup times t as address setup before clk rise 1.4 ? 1.4 ? 1.5 ? ns t ads adsc , adsp setup before clk rise 1.4 ? 1.4 ? 1.5 ? ns t advs adv setup before clk rise 1.4 ? 1.4 ? 1.5 ? ns t wes gw , bwe , bw x setup before clk rise 1.4 ? 1.4 ? 1.5 ? ns t ds data input setup before clk rise 1.4 ? 1.4 ? 1.5 ? ns t ces chip enable setup before clk rise 1.4 ? 1.4 ? 1.5 ? ns hold times t ah address hold after clk rise 0.4 ? 0.4 ? 0.5 ? ns t adh adsp , adsc hold after clk rise 0.4 ? 0.4 ? 0.5 ? ns t advh adv hold after clk rise 0.4 ? 0.4 ? 0.5 ? ns t weh gw , bwe , bw x hold after clk rise 0.4 ? 0.4 ? 0.5 ? ns t dh data input hold after clk rise 0.4 ? 0.4 ? 0.5 ? ns t ceh chip enable hold after clk rise 0.4 ? 0.4 ? 0.5 ? ns notes 16. timing reference level is 1.25 v when v ddq = 2.5 v. 17. test conditions shown in (a) of figure 3 on page 22 unless otherwise noted. 18. this part has an internal voltage regulator; t power is the time that the power is supplied above v dd (minimum) initially before a read or write operation can be initiated. 19. t chz , t clz , t oelz , and t oehz are specified with ac test conditions shown in part (b) of figure 3 on page 22 . transition is measured 200 mv from steady-state voltage. 20. at any possible voltage and temperature, t oehz is less than t oelz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not imply a bu s contention condition, but reflect paramet ers guaranteed over worst case user condi tions. device is designed to achieve high z before low z under the same system conditions. 21. this parameter is sampled and not 100% tested. [+] feedback
cy7c1480bv25 cy7c1482bv25, cy7c1486bv25 document number: 001-15143 rev. *h page 24 of 34 switching waveforms figure 4. read cycle timing [22] t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a1 t ceh t ces gw, bwe, bwx d ata out (q) high-z t clz t doh t co adv t oehz t co single read burst read t oev t oelz t chz adv suspends burst. burst wraps around to its initial state t advh t advs t weh t wes t adh t ads q(a2) q(a2 + 1) q(a2 + 2) q(a1) q(a2) q(a2 + 1) q(a2 + 3) a2 a3 deselect cycle burst continued with new base address dont care undefined note 22. on this diagram, when ce is low: ce 1 is low, ce 2 is high, and ce 3 is low. when ce is high: ce 1 is high, ce 2 is low, or ce 3 is high. [+] feedback
cy7c1480bv25 cy7c1482bv25, cy7c1486bv25 document number: 001-15143 rev. *h page 25 of 34 figure 5. write cycle timing [23, 24] switching waveforms (continued) t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a1 t ceh t ces bwe, bw x d ata out (q) high-z adv burst read burst write d(a2) d(a2 + 1) d(a2 + 1) d(a1) d(a3) d(a3 + 1) d(a3 + 2) d(a2 + 3) a2 a3 data in (d) extended burst write d(a2 + 2) single write t adh t ads t adh t ads t oehz t advh t advs t weh t wes t dh t ds gw t weh t wes byte write signals are ignored for rst cycle when adsp initiates burst adsc extends burst adv suspends burst dont care undefined notes 23. on this diagram, when ce is low: ce 1 is low, ce 2 is high, and ce 3 is low. when ce is high: ce 1 is high, ce 2 is low, or ce 3 is high. 24. full width write can be initiated by either gw low; or by gw high, bwe low, and bw x low. [+] feedback
cy7c1480bv25 cy7c1482bv25, cy7c1486bv25 document number: 001-15143 rev. *h page 26 of 34 figure 6. read/write cycle timing [25, 26, 27] switching waveforms (continued) t cyc t cl clk adsp t adh t ads address t ch oe adsc ce t ah t as a2 t ceh t ces d ata out (q) high-z adv single write d(a3) a4 a5 a6 d(a5) d(a6) data in (d) burst read back-to-back reads high-z q(a2) q(a1) q(a4) q(a4+1) q(a4+2) t weh t wes q(a4+3) t oehz t dh t ds t oelz t clz t co back-to-back writes a1 dont care undefined a3 bwe, bw x notes 25. on this diagram, when ce is low: ce 1 is low, ce 2 is high, and ce 3 is low. when ce is high: ce 1 is high, ce 2 is low, or ce 3 is high. 26. the data bus (q) remains in high z following a writ e cycle, unless a new read access is initiated by adsp or adsc . 27. gw is high. [+] feedback
cy7c1480bv25 cy7c1482bv25, cy7c1486bv25 document number: 001-15143 rev. *h page 27 of 34 figure 7. zz mode timing [28, 29] switching waveforms (continued) t zz i supply clk zz t zzrec a ll inputs (except zz) dont care i ddzz t zzi t rzzi outputs (q) high-z deselect or read only notes 28. device must be deselected when entering zz mode. see truth table on page 11 for all possible signal conditions to deselect the device. 29. dqs are in high z when exiting zz sleep mode. [+] feedback
cy7c1480bv25 cy7c1482bv25, cy7c1486bv25 document number: 001-15143 rev. *h page 28 of 34 ordering code definitions ordering information cypress offers other versions of this type of product in many different configurations and feat ures. the following table contai ns only the list of parts that are currently available. for a complete listing of all optio ns, visit the cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products or contact your local sales representative. cypress maintains a worldwide network of offices, solution center s, manufacturer's representatives and distributors. to find th e office closest to you, visit us at http://www.cypress.com /go/datasheet/offices . speed (mhz) ordering code package diagram part and package type operating range 167 CY7C1480BV25-167AXC 51-8505 0 100-pin tqfp (14 20 1.4 mm) pb-free commercial cy7c1480bv25-167bzxc 51-85165 165-ball fbga (15 17 1.4 mm) pb-free 200 cy7c1480bv25-200bzc 51-85165 165-ball fbga (15 17 1.4 mm) commercial 250 cy7c1480bv25-250bzi 51-85165 165-ball fbga (15 17 1.4 mm) industrial temperature range: x = c or i c = commercial; i = industrial pb-free package type: xx = a or bz a = 100-pin tqfp bz = 165-ball fbga frequency range: xxx = 167 mhz or 200 mhz or 250 mhz voltage: 2.5 v die revision: errata fix pcn084636 1480 = scd, 2 mb 36 (72 mb) marketing code: 7c = sram company id: cy = cypress x cy 1480 b - xxx xx 7c v25 x [+] feedback
cy7c1480bv25 cy7c1482bv25, cy7c1486bv25 document number: 001-15143 rev. *h page 29 of 34 package diagrams figure 8. 100-pin tqfp (14 20 1.4 mm), 51-85050 51-85050 *d [+] feedback
cy7c1480bv25 cy7c1482bv25, cy7c1486bv25 document number: 001-15143 rev. *h page 30 of 34 figure 9. 165-ball fbga (15 17 1.4 mm), 51-85165 package diagrams (continued) 51-85165 *b [+] feedback
cy7c1480bv25 cy7c1482bv25, cy7c1486bv25 document number: 001-15143 rev. *h page 31 of 34 figure 10. 209-ball fbga (14 22 1.76 mm), 51-85167 package diagrams (continued) 51-85167 *a [+] feedback
cy7c1480bv25 cy7c1482bv25, cy7c1486bv25 document number: 001-15143 rev. *h page 32 of 34 acronyms document conventions units of measure acronym description bga ball grid array cmos complementary metal oxide semiconductor fbga fine-pitch ball grid array i/o input/output jtag joint test action group lsb least significant bit msb most significant bit lsbu logical single bit upset lmbu logical multi bit upset oe output enable sel single event latch up sram static random access memory tap test access port tck test clock tms test mode select tdi test data-in tdo test data-out tqfp thin quad flat pack ttl transistor-transistor logic symbol unit of measure ns nano seconds mv milli volts vvolts a micro amperes ma milli amperes mm milli meter ms milli seconds mhz mega hertz pf pico farad wwatts c degree celcius ? ohms % percent [+] feedback
cy7c1480bv25 cy7c1482bv25, cy7c1486bv25 document number: 001-15143 rev. *h page 33 of 34 document history page document title: cy7c1480bv25/cy7c1482 bv25/cy7c1486bv25, 72-mbit (2 m 36/4 m 18/1 m 72) pipelined sync sram document number: 001-15143 rev. ecn no. submission date orig. of change description of change ** 1024385 see ecn vkn/kkvtmp new data sheet *a 1562944 see ecn vkn/aesa removed 1.8v i/o offering from the data sheet *b 1897447 see ecn vkn/aesa added footno te 14 related to idd *c 2082487 see ecn vkn converted from preliminary to final *d 2159486 see ecn vkn/pyrs minor change-moved to the external web *e 2899725 03/26/2010 njy removed inactive parts fr om the ordering information table; updated package diagrams. *f 2957481 06/21/2010 vkn included soft error immunity data modified the disclaimer for the ordering information. included ?cy7c1480bv25-167bzxc? in the ordering information table added ordering code definitions *g 3211551 04/19/2011 njy updated ordering information . updated package diagrams . added units of measure . updated in new template. *h 3244686 04/29/2011 njy updated ordering information . [+] feedback
document number: 001-15143 rev. *h revised may 4, 2011 page 34 of 34 nobl and no bus latency are trademarks of cypress semiconductor corporation. zbt is a trademark of integrated device technology , inc. all products and company names mentioned in this document may be the trademarks of their respective holders. cy7c1480bv25 cy7c1482bv25, cy7c1486bv25 ? cypress semiconductor corporation, 2007-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

▲Up To Search▲

Price & Availability of CY7C1480BV25-167AXC

	To Download CY7C1480BV25-167AXC Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .